The present invention relates generally to a non-volatile semiconductor memory device and, more particularly, to a self-aligned split-gate flash memory cell and its contactless memory array for mass storage applications.
A semiconductor memory array is in general arranged in a matrix form with a plurality of bit lines being formed transversely to a plurality of word lines. Basically, the binary data are stored in a memory element as is called a cell, the basic logic function is used to implement an array architecture. For a flash memory array, the memory element in a matrix is often configured to be a NOR-type or a NAND-type. Based on the cell structure, the flash memory cells of the prior arts can be basically divided into two categories: a stack gate structure and a split-gate structure.
The stack-gate flash memory cell is known to be a one-transistor cell, in which the gate length of a cell can be defined by using a minimum-feature-size (F) of technology used. Therefore, the stack-gate flash memory cell is often used in existing high-density memory system. The stack-gate flash memory cells can be interconnected in series to form a high-density NAND-type array with common source/drain diffusion regions. However, the read speed is relatively slow for a NAND-type array due to the series resistance of the configuration. Moreover, a NAND-type flash memory cell is programmed by Fowler-Nordheim tunneling across the thin tunneling-oxide layer between the floating-gate and the common source/drain diffusion region and its programming speed is relatively slow. In addition, when the gate length of a stack-gate flash memory cell in a NAND-type array is further scaled down, the junction depth of common-source/drain diffusion regions must be scaled accordingly, and the overlapped region between the floating gate and the common-source/drain diffusion region becomes smaller, resulting in a further slow process for programming, reading and erasing.
The stack-gate flash memory cells can be connected with common-source diffusion lines and the drain diffusion regions in each column being connected to a bit line through contacts for a NOR-type flash memory array. The read speed of a NOR-type flash memory array is much faster as compared to that of a NAND-type flash memory array. A stack-gate flash memory cell in a NOR-type flash memory array is in general programmed by channel hot-electron injection and its programming speed is much faster than that of a NAND-type flash memory array; however, the programming power is large and the programming efficiency is low. The erasing speed of a NOR-type flash memory array is quite similar to that of a NAND-type flash memory array and is limited by Fowler-Nordheim tunneling across the thin tunneling-oxide layer between the floating-gate and the common-source diffusion line; however, the over-erase problem needs a complex circuitry to do verification. Moreover, as the gate length of a stack-gate flash memory cell is further scaled, the punch-through effect becomes a major concern for channel hot-electron injection as a programming method. In addition, the cell size of a NOR-type flash memory array is about twice that of a NAND-type flash memory array due to the bit-line contact. Therefore, the contactless flash memory array by taking advantages of a NOR-type flash memory array becomes a major trend of technology development.
FIG. 1 shows a typical contactless flash memory array, in which a plurality of bit lines (BL0xcx9cBL6) are formed by using the common buried diffusion lines; the stack-gate flash memory cells (100xcx9c129) in each column are arranged between the bit lines; the control-gates in each row are connected to form a word line (WL); and a plurality of word lines are perpendicular to the plurality of bit lines. It is clearly seen that the cell size of FIG. 1 can be made to be comparable with that of a NAND array due to the contactless structure used; the read speed of FIG. 1 is better than that of a NAND array and is inferior to that of a NOR-type array due to the larger bit-line capacitance with respect to the semiconductor substrate. Since the stack-gate structure in the channel-width direction must be etched to have an independent floating-gate for each cell, elaborate engineering works must be done without trenching the buried diffusion bit lines and the semiconductor substrate between the word lines. Moreover, the isolation of cells between the neighboring word lines is performed by ion-implantation, resulting in the further increase of the bit-line capacitance and the reduction of cell width. Similarly, the gate length of the stack-gate flash memory cell is difficult to be scaled down due to the punch-through effect and the junction depth of the buried bit-line diffusion region can""t be easily scaled without increasing the bit-line resistance and decreasing the erasing speed. A typical example for implementing a high-density memory array shown in FIG. 1 may refer to U.S. Pat. No. 5,654,917, in which a high parasitic capacitance between the word lines and the bit lines can be observed.
A self-aligned split-gate flash memory cell of the present invention is formed on a shallow-trench-isolation (STI) structure being formed on a semiconductor substrate of a first conductivity type. The shallow-trench-isolation structure comprises an active region being formed between two parallel STI regions, in which a first conductive layer being formed on a thin tunneling-dielectric layer is located in the active region and the raised filed-oxide (FOX) layer is formed on each of parallel STI regions. A self-aligned split-gate flash memory cell can be divided into three regions: a common-source region, a gate region, and a common-drain region, in which the gate region is located between the common-source region and the common-drain region. The gate region comprises a control-gate with its gate length being defined by a sidewall dielectric spacer formed over a sidewall of the common-source region and is further divided into two sub-regions: a floating-gate region and a select-gate region, in which the floating-gate region comprises a floating-gate transistor being formed on a thin tunneling-dielectric layer with a floating-gate length being defined by a sidewall dielectric spacer formed over the same sidewall of the common-source region; the select-gate region comprises a select-gate transistor being formed on a gate-dielectric layer and is located near the common-drain region. The floating-gate transistor comprises an intergate dielectric layer being formed over the floating-gate and a nitrided thermal poly-oxide layer being formed over a sidewall to separate from the control-gate. The floating-gate length being defined by a sidewall dielectric spacer can be etched to form a steep floating-gate structure or a one-side tapered floating-gate structure and the nitrided thermal poly-oxide layer being formed over the sidewall can be acted as a tunneling-dielectric layer for erasing the stored electrons in the floating-gate to the control-gate. An implanted region being formed under the gate-dielectric layer of the select-gate transistor comprises a shallow implant region of a first conductivity type for threshold-voltage adjustment of the select-gate transistor and a deep implant region of a first conductivity type for forming a punch-through stop. The common-source region comprises a common-source diffusion region of a second conductivity type being implanted with doping impurities in a self-aligned manner into a semiconductor substrate of the active region, a first flat bed being formed by a common-source diffusion region and the first etched raised field-oxide layers, a first sidewall dielectric spacer being formed over a sidewall of the gate region and on a portion of the first flat bed, a common-source conductive bus line capped with a first metal-silicide layer being formed over the first flat bed outside of the first sidewall dielectric spacer, and a first planarized thick-oxide layer being formed over the first sidewall dielectric spacer and the first metal-silicide layer. The common-drain region comprises a common-drain diffusion region of a second conductivity type being implanted with doping impurities in a self-aligned manner into a semiconductor substrate of the active region, a second flat bed being formed by a common-drain diffusion region and the second etched raised field-oxide layers, a second sidewall dielectric spacer being formed over a sidewall of the gate region and on a portion of the second flat bed, a common-drain conductive bus line capped with a second metal-silicide layer being formed over the second flat bed outside of the second sidewall dielectric spacer, and a second planarized thick-oxide layer being formed over the second sidewall dielectric spacer and the second metal-silicide layer. The control gate together with a first interconnect metal layer being acted as a word line is patterned transversely to the common-source/drain conductive bus line and etched simultaneously by a hard masking layer being formed by a masking dielectric layer being aligned above the active region and its two sidewall dielectric spacers.
A contactless self-aligned split-gate flash memory array of the present invention comprises a plurality of parallel shallow-trench-isolation (STI) regions and a plurality of active regions being formed alternately on a semiconductor substrate of a first conductivity type, and each of the plurality of parallel STI regions is filled with a raised field-oxide layer; a plurality of virtual gate regions and a plurality of common-source regions being alternately formed by a masking photoresist step and being transversely to the plurality of parallel STI regions, and each of the plurality of virtual gate regions is divided into three regions: two self-aligned split-gate regions being located in each side portion and a common-drain region being located between the self-aligned split-gate regions; and a plurality of word lines being formed transversely to the plurality of common-source/drain regions and above the plurality of active regions, and each of the plurality of word lines being connected to the control-gates of the self-aligned split-gate regions in a row. The self-aligned split-gate region comprises a plurality of self-aligned split-gate flash memory cells in a column, and each of the plurality of self-aligned split-gate flash memory cells being aforementioned. Each of the plurality of common-source regions comprises a plurality of common-source diffusion regions of a second conductivity type being formed by implanting doping impurities in a self-aligned manner into the semiconductor substrate of the plurality of active regions along the common-source region; a first flat bed being formed alternately by a common-source diffusion region and a first etched raised field-oxide layer; a pair of first sidewall dielectric spacers being formed over the sidewalls of the neighboring virtual gate regions and on a portion of the first flat bed; a common-source conductive bus line is formed over the first flat bed between the pair of first sidewall dielectric spacers; a first metal-silicide layer is formed over the common-source conductive bus line; and a first planarized thick-oxide layer is formed over the first metal-silicide layer and the pair of first sidewall dielectric spacers. The common-drain region comprises a plurality of common-drain diffusion regions of a second conductivity type being formed by implanting doping impurities in a self-aligned manner into the semiconductor substrate of the plurality of active regions along the common-drain region; a second flat bed being formed alternately by a common-drain diffusion region and a second etched raised field-oxide layer; a pair of second sidewall dielectric spacers are formed over the sidewalls of the neighboring self-aligned split-gate regions and on a portion of the second flat bed; a common-drain conductive bus line is formed over the second flat bed between the pair of second sidewall dielectric spacers, a second metal-silicide layer is formed over the common-drain conductive bus line; and a second planarized thick-oxide layer is formed over the second metal-silicide layer and the pair of second sidewall dielectric spacers. Each of the plurality of word lines comprises a first interconnect metal layer being integrated with a plurality of control-gates in a row and is patterned and etched simultaneously with the plurality of control-gates by a hard masking layer being formed by a masking dielectric layer being aligned to the active region and its two sidewall dielectric spacers.